`include "top.v"

module testbench;
//Para simulacao apenas:
reg clk = 0;
reg [15:0] inst_in;
reg rstN = 1;
wire [15:0] bus;

top processador(clk,
                rstN,
                inst_in,
                bus);

//Inicio do testbench:
always #1 clk = !clk;

initial $dumpfile("testbench.vcd");
initial $dumpvars(0, testbench);

/*
Programa de simulação:
    1) Armazena o numero 6 no registrador R3;
    2) Armazena o numero 2 no reigstrador R4;
    3) R3 = R3 + R4;
    4) R3 = R3 - R4;
    5) R7 = R4;
    5) R4 = R4 ~& R3;
    6) R7
*/

initial begin
#0 rstN = 0;
#2 rstN = 1;
#0 inst_in = 16'b1010110000000110; //R3 = 6
#8 inst_in = 16'b1011000000000010; //R4 = 2
#8 inst_in = 16'b0000111000000000; //R3 += R4;
#8 inst_in = 16'b0010111000000000; //R3 -= R4;
#8 inst_in = 16'b1111111000000000; //R7 = R4;
#8 inst_in = 16'b0101000110000000; //R4 ~&= R3;
#8 inst_in = 16'b1000000000000000; //Out R7

#60 $finish;

end



endmodule
